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ST
Sitronix
Features :
Display driving bias : static to 1/5 Power supply for logic : 2.7V ~ 5.5V Power supply for LCD voltage (V0~VSS) : 3V ~ 7V Dot matrix LCD driver with two 48 channel outputs Bias voltage (V0 ~ V4) Input/Output signals
Input : Serial display data and control pulse from controller IC Output : 48 X 2 channels waveform for LCD driving
ST7921
96CH Segment Driver For Dot Matrix LCD
General Description :
ST7921 is a segment driver for dot matrix type LCD display. It features 96 channels with 48 X 2 bits bi-directional shift registers, data latches, LCD drivers and logic control circuits. It is fabricated by high voltage CMOS process with low current consumption. The ST7921 can convert serial data received from an LCD controller, such as ST7920, into parallel data and send out LCD driving waveforms to the LCD panel. The ST7921 is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCD. The LSI can be used as segment driver.
Ver 1.6
1/11
2005/05/24
ST7921
ST7921 Functional Block
S1...............................S48
S49...............................S96
V1 V2 V3 V4
SEGMENT DRIVER
SEGMENT DRIVER VDD VSS V0
DATA LATCH(48bits)
DATA LATCH(48bits)
BIDIRECTIONAL SHIFTER(48bits)
BIDIRECTIONAL SHIFTER(48bits)
M CL1 CL2
CONTOL
DL1 SHL1 DR1
DL2 SHL2 DR2
Ver 1.6
2/11
2005/05/24
ST7921
Pin Description :
Pin Name
VDD VSS
Purpose
POWER GROUND
Description
for logic for logic
I/O
N/A N/A
V0 V2 V3
LCD Power
for LCD driving voltage
I
S1-S48 SHL1
segment direction
LCD driver output for part 1 direction control for part 1 segments If SHL1 = 1 then DL1=out, DR1=in If SHL1 = 0 then DL1=in, DR1=out LCD driver output for part 2 direction control for part 2 segments If SHL2 = 1 then DL2=out, DR2=in If SHL2 = 0 then DL2=in, DR2=out Alternate the LCD driving waveform latch the data after shift is completed shift the data into the segments
O I
DL1, DR1
data in /out
I/O
S49-S96 SHL2
segment direction
O I
DL2, DR2
data in/out
I/O
M CL1 CL2
alternation latch clock shift clock
I I I
Ver 1.6
3/11
2005/05/24
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 3
8 2
8 1
8 0
.......
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7 5 6
95 9 6 9 7 9 8 9 9 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7
5 5 5 4 5 3 5 2 5 1 5 0 4 9
(0,0 )
4 7 4 6
Size: 4720x2560 um Coordinate: center Min. PAD Pitch: 120um
Circle here to find the first PAD
4 4 4 3 4 2 "GSM792E" Marking: Easy to find the PAD 4 1 4 0
Pad Arrangement
10 8 10 9 11 0
G792E
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5
3 9 3 7 3 8
.......
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
* chip substrate must connect to VSS
2
4 5
ST7921
Ver 1.6
4/11
4 8
2005/05/24
ST7921
Bonding Description
Pad No. Pad Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 S[50] S[51] S[52] S[53] S[54] S[55] S[56] S[57] S[58] S[59] S[60] S[61] S[62] S[63] S[64] S[65] S[66] S[67] S[68] S[69] S[70] S[71] S[72] S[73] S[74] S[75] S[76] S[77] X -2240 -2110 -1980 -1860 -1740 -1620 -1500 -1380 -1260 -1140 -1020 -900 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1020 Y -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 Pad No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Pad Name S[78] S[79] S[80] S[81] S[82] S[83] S[84] S[85] S[86] S[87] S[88] S[89] S[90] S[91] S[92] S[93] S[94] S[95] S[96] S[48] S[47] S[46] S[45] S[44] S[43] S[42] S[41] S[40] X 1140 1260 1380 1500 1620 1740 1860 1980 2110 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 2240 Y -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1030 -900 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1030
Ver 1.6
5/11
2005/05/24
ST7921
Pad No. Pad Name 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 S[39] S[38] S[37] S[36] S[35] S[34] S[33] S[32] S[31] S[30] S[29] S[28] S[27] S[26] S[25] S[24] S[23] S[22] S[21] S[20] S[19] S[18] S[17] S[16] S[15] S[14] S[13] S[12]
X 2240 2110 1980 1860 1740 1620 1500 1380 1260 1140 1020 900 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 -780 -900 -1020
Y 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160
Pad No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
Pad Name S[11] S[10] S[9] S[8] S[7] S[6] S[5] S[4] S[3] S[2] S[1] V0 V2 V3 VSS VDD CL1 SHL1 SHL2 CL2 DL1 DR1 DL2 DR2 M S[49]
X -1140 -1260 -1380 -1500 -1620 -1740 -1860 -1980 -2110 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240 -2240
Y 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1030 890 750 610 475 340 210 80 -50 -180 -310 -440 -580 -720 -860 -1010
Ver 1.6
6/11
2005/05/24
ST7921
Functional Description :
Clock The CL1 is the clock to latch data on the falling edge. It latches the data input from the bi-directional shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit of the register to the latch circuit.
Shift Registers And Data I/O The ST7921 supplies two sets of 48-bit shift register, which controls the shift direction by SHL1 & SHL2. The SHL1 controls the 1st 48-bit shift register, and SHL2 controls the 2nd 48-bit shift register. When SHL1 is connected to VDD, the 1st shift direction is from S48 to S1; when SHL1 is connected to VSS, the shift direction changes from S1 to S48. When SHL2 is connected to VDD, the 2nd shift direction is from S96 to S49; when SHL2 is connected to VSS, the shift direction changes from S49 to S96. The DL1, DR1, DL2, DR2 are data input or output option function.
Shift Direction of Channel 1 SHL1
0 1
Shift Direction
S1 S48 S48 S1
DL1
IN OUT
DR1
OUT IN
Shift Direction of Channel 2 SHL2
0 1
Shift Direction
S49 S96 S96 S49
DL2
IN OUT
DR2
OUT IN
Ver 1.6
7/11
2005/05/24
ST7921
LCD Output Waveforms :
Output of LATCH (DATA)
M
V0 V2 Output (S1 ~ S80) V3 VSS VSS
V0 V2 V3
Timing Characteristics :
VIH CL2 VIL TR TWCKH TF TDH TSU Data in (DL1, DL2) (DR1, DR2)
TWCKL
TD VOH Data out (DL1, DL2) (DR1, DR2) TSL VOL TLS TLS
CL1 TWCKH TR TSU M
Ver 1.6
8/11
2005/05/24
ST7921
D.C Characteristics:
Symbol
VDD VLCD VIH VIL ILKG VOH VOL IDD IV
Parameter
Operating Voltage Driver Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Operating Current Leakage Current
Test Condition Min.
V0-VSS VIN = 0 ~ VDD IOH = -0.4mA IOL = +0.4mA FCL2 = 400KHZ VIN = VDD ~ VSS 2.7 3 0.7VDD 0 -5 VDD-0.4 -10
Typ. Max. Unit
280 5.5 7 VDD 0.3VDD 5 0.4 460 10 V V V V uA V V uA uA
Applicable pin
CL1,CL2,M,SHL1,SHL2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 V1~V4, S1~S80 VDD,V0 V1 ~ V4
A.C Characteristics :
Symbol
FCL TWCKH TWCKL TSL TLS TR/TF TSU TDH TD
Parameter
Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Clock Set-up Time Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time
Test Condition Min. Max. Unit
CL2 CL1 CL = 15 PF CL1 CL2 800 800 500 500 300 300 400 200 500 KHZ ns ns ns ns ns ns ns ns
Applicable pin
CL2 CL1,CL2 CL2 CL1,CL2 CL1,CL2 CL1,CL2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2
Maximum Absolute Ratings :
Symbol
VDD TOPR TSTG
Parameters
Supply Voltage Operating Temperature Storage Temperature
Min.
-0.3 -20 -55
Max.
7 85 125
Unit
V
0
C C
0
Ver 1.6
9/11
2005/05/24
Dot Matrix LCD Panel
Application Circuit : (2Line x 16 Chinese Word)
Com 1-32
Seg 1-64 Dout
DL1 VDD SHL1 SHL2 VSS V0
Seg 1-96
ST7921
V2 V3
DR2 DL2 DR1 CL1 CL2 M
DL1 VDD SHL1 SHL2 VSS V0
Seg 1-96
ST7921
V2 V3
DR2 DL2 DR1 CL1 CL2 M
ST7920
DB0-DB7
VDD VSS CL2 CL1 M V0 V1 V2 V3 V4
Vcc(+5V/+3V) To MPU
VR
Regsister
Regsister
Regsister
Regsister
Regsister
VSS
ST7921
Note:Regsister=2.2K~10K ohm
VR=1K~30Kohm
Ver 1.6
10/11
2005/05/24
ST7921
ST7921 Specification Revision History Version
C1.6
Date
2005/05/24
Description
1. Modify Operating Temperature=-200C ~850C
Ver 1.6
11/11
2005/05/24

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